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2-channel, 2.35 v to 5.25 v 250 ksps, 10-/12-bit adcs ad7911 / ad7921 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ?2004C2011 analog devices, inc. all rights reserved. features fast throughput rate: 250 ksps specified for v dd of 2.35 v to 5.25 v low power: 4 mw typ at 250 ksps with 3 v supplies 13.5 mw typ at 250 ksps with 5 v supplies wide input bandwidth: 71 db minimum snr at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface: spi?/qspi?/microwire?/dsp compatible standby mode: 1 a maximum 8-lead tsot package 8-lead msop package applications battery-powered systems: personal digital assistants medical instruments mobile communications instrumentation and control systems data acquisition systems high speed modems optical sensors general description the ad7911/ad7921 1 are 10-bit and 12-bit, high speed, low power, 2-channel successive approximation adcs, respectively. the parts operate from a single 2.35 v to 5.25 v power supply and feature throughput rates of up to 250 ksps. the parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 6 mhz. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs , and the conversion is also initiated at this point. there are no pipeline delays associated with the part. the channel to be converted is selected through the din pin, and the mode of operation is controlled by cs . the serial data stream from the dout pin has a channel identifier bit, which provides information about the converted channel. 1 protected by u.s. patent number 6,681,332. functional block diagram 04350-0-001 t/h control logic 10-/12-bit successive approximation adc gnd v dd ad7911/ad7921 v in0 v in1 sclk dout cs din mux figure 1. the ad7911/ad7921 use advanced design techniques to achieve very low power dissipation at high throughput rates. the reference for the part is taken internally from v dd , thereby allowing the widest dynamic input range to the adc. the analog input range for the part, therefore, is 0 to v dd . the conversion rate is determined by the sclk signal. product highlights 1. 2-channel, 250 ksps, 10-/12-bit adcs in tsot package. 2. low power consumption. 3. flexible power/serial clock speed management. the conversion rate is determined by the serial clock; conversion time is reduced when the serial clock speed is increased. the parts also feature a power-down mode to maximize power efficiency at lower throughput rates. average power consumption is reduced when the power- down mode is used while not converting. current consumption is 1 a maximum and 50 na typically when in power-down mode. 4. reference derived from the power supply. 5. no pipeline delay. the parts feature a standard successive approximation adc with accurate control of the sampling instant via a cs input and once-off conversion control.
ad7911/ad7921 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 ad7911 specifications ................................................................. 3 ad7921 specifications ................................................................. 5 timing specifications .................................................................. 7 timing diagrams .......................................................................... 7 timing examples .......................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 ter mi nolo g y .................................................................................... 11 typical performance characteristics ........................................... 13 circuit information ........................................................................ 15 converter operation .................................................................. 15 adc transfer function ............................................................. 15 typical connection diagram ................................................... 16 analog input ............................................................................... 16 digital inputs .............................................................................. 17 din input .................................................................................... 17 dout output ............................................................................ 17 modes of operation ....................................................................... 18 normal mode .............................................................................. 18 power-down mode .................................................................... 18 power-up time .......................................................................... 19 power vs. throughput rate ....................................................... 20 serial interface ................................................................................ 21 microprocessor interfacing ....................................................... 22 application hints ........................................................................... 24 grounding and layout .............................................................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 5/11rev. 0 to rev. a updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 4/04revision 0: initial version
ad7911/ad7921 rev. a | page 3 of 28 specifications ad7911 specifications temperature range for a grade from ?40c to +85c. v dd = 2.35 v to 5.25 v, f sclk = 5 mhz, f sample = 250 ksps; t a = t min to t max , unless otherwise noted. table 1. parameter a grade 1 unit test conditions/comments dynamic performance f in = 100 khz sine wave signal-to- noise and distortion (sinad) 2 61 db min total harmonic distortion (thd) 2 ?71 db max peak harmonic or spurious noise (sfdr) 2 ?72 db max intermodulation distortion (imd) 2 second-order terms ?82 db typ fa = 100.73 khz, fb = 90.7 khz third-order terms ?83 db typ fa = 100.73 khz, fb = 90.7 khz aperture delay 10 ns typ aperture jitter 30 ps typ channel-to-channel isolation 2 ?90 db typ full power bandwidth 8.5 mhz typ @ 3 db 1.5 mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 2 0.5 lsb max differential nonlinearity 2 0.5 lsb max guaranteed no missed codes to 10 bits offset error 2 0.5 lsb max offset error match 2 , 3 0.3 lsb max gain error 2 0.5 lsb max gain error match 2 , 3 0.3 lsb max total unadjusted error (tue) 2 0.5 lsb max analog input input voltage ranges 0 to v dd v dc leakage current 0.3 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 0.7 (v dd ) v min 2.35 v v dd 2.7 v 2 v min 2.7 v < v dd 5.25 v input low voltage, v inl 0.3 v max v dd = 2.35 v 0.2 (v dd ) v max 2.35 v < v dd 2.7 v 0.8 v max 2.7 v < v dd 5.25 v input current, i in , sclk pin 0.3 a max v in = 0 v or v dd input current, i in , cs pin 0.3 a max input current, i in , din pin 0.3 a max input capacitance, c in 5 pf max logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a, v dd = 2.35 v to 5.25 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 0.3 a max floating-state output capacitance 3 5 pf max output coding straight (natural) binary see notes at end of table.
ad7911/ad7921 rev. a | page 4 of 28 parameter a grade 1 unit test conditions/comments conversion rate conversion time 2.8 s max 14 sclk cycles with sclk at 5 mhz track-and-hold acquisition time 2 290 ns max throughput rate 250 ksps max power requirements v dd 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 3 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.5 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 4 ma max v dd = 4.75 v to 5.25 v, f sample = 250 ksps 2 ma max v dd = 2.35 v to 3.6 v, f sample = 250 ksps full power-down mode (static) 1 a ma x sclk on or off, typically 50 na full power-down mode (dynamic) 0.38 ma typ v dd = 5 v, f sclk = 5 mhz, f sample = 25 ksps 0.2 ma typ v dd = 3 v, f sclk = 5 mhz, f sample = 25 ksps power dissipation 4 normal mode (operational) 20 mw max v dd = 5 v, f sample = 250 ksps 6 mw max v dd = 3 v, f sample = 250 ksps full power-down 5 w max v dd = 5 v 1 operational from v dd = 2 v, with v ih = 1.9 v minimum and v il = 0.1 v maximum. 2 see the terminology section. 3 guaranteed by characterization. 4 see the power vs. throughput rate section.
ad7911/ad7921 rev. a | page 5 of 28 ad7921 specifications temperature range for a grade from ?40c to +85c. v dd = 2.35 v to 5.25 v, f sclk = 5 mhz, f sample = 250 ksps; t a = t min to t max , unless otherwise noted. table 2. parameter a grade 1 unit test conditions/comments dynamic performance f in = 100 khz sine wave signal-to-noise and distortion (sinad) 2 70 db min 72 db typ signal-to-noise ratio (snr) 2 71 db min 72.5 db typ total harmonic distortion (thd) 2 ?81 db typ peak harmonic or spurious noise (sfdr) 2 ?84 db typ intermodulation distortion (imd) 2 second-order terms ?84 db typ fa = 100.73 khz, fb = 90.72 khz third-order term ?86 db typ fa = 100.73 khz, fb = 90.72 khz aperture delay 10 ns typ aperture jitter 30 ps typ channel-to-channel isolation 2 ?90 db typ full power bandwidth 8.5 mhz typ @ 3 db 1.5 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1.5 lsb max differential nonlinearity 2 ?0.9/+1.5 lsb max guaranteed no missed codes to 12 bits offset error 2 1.5 lsb max 0.5 lsb typ offset error match 2 , 3 0.5 lsb max gain error 2 2 lsb max 0.3 lsb typ gain error match 2 , 3 1 lsb max total unadjusted error (tue) 2 1.5 lsb max analog input input voltage ranges 0 to v dd v dc leakage current 0.3 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 0.7 (v dd ) v min 2.35 v v dd 2.7 v 2 v min 2.7 v < v dd 5.25 v input low voltage, v inl 0.3 v max v dd = 2.35 v 0.2 (v dd ) v max 2.35 v < v dd 2.7 v 0.8 v max 2.7 v < v dd 5.25 v input current, i in , sclk pin 0.3 a max v in = 0 v or v dd input current, i in , cs pin 0.3 a max input current, i in , din pin 0.3 a max input capacitance, c in 3 5 pf max logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 2.35 v to 5.25 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 0.3 a max floating-state output capacitance 3 5 pf max output coding straight (natural) binary see notes at end of table.
ad7911/ad7921 rev. a | page 6 of 28 parameter a grade 1 unit test conditions/comments conversion rate conversion time 3.2 s max 16 sclk cycles with sclk at 5 mhz track-and-hold acquisition time 2 290 ns max throughput rate 250 ksps max see the serial interface section power requirements v dd 2.35/5.25 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) 3 ma typ v dd = 4.75 v to 5.25 v, sclk on or off 1.5 ma typ v dd = 2.35 v to 3.6 v, sclk on or off normal mode (operational) 4 ma max v dd = 4.75 v to 5.25 v, f sample = 250 ksps 2 ma max v dd = 2.35 v to 3.6 v, f sample = 250 ksps full power-down mode (static) 1 a ma x sclk on or off, typically 50 na full power-down mode (dynamic) 0.4 ma typ v dd = 5 v, f sclk = 5 mhz, f sample = 25 ksps 0.22 ma typ v dd = 3 v, f sclk = 5 mhz, f sample = 25 ksps power dissipation 4 normal mode (operational) 20 mw max v dd = 5 v, f sample = 250 ksps 6 mw max v dd = 3 v, f sample = 250 ksps full power-down 5 w max v dd = 5 v 3 w max v dd = 3 v 1 operational from v dd = 2 v, with v ih = 1.9 v minimum and v il = 0.1 v maximum. 2 see the terminology section. 3 guaranteed by characterization. 4 see the power vs. throughput rate section.
ad7911/ad7921 rev. a | page 7 of 28 timing specifications guaranteed by characterization. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. v dd = 2.35 v to 5.25 v; t a = t min to t max , unless otherwise noted. table 3. parameter limit at t min , t max unit description f sclk 1 10 khz min 2 5 mhz max t convert 16 t sclk ad7921 14 t sclk ad7911 t quiet 30 ns min minimum quiet time required betw een bus relinquish and start of next conversion t 1 15 ns min minimum cs pulse width t 2 10 ns min cs to sclk setup time t 3 3 30 ns max delay from cs until dout three-state is disabled t 4 3 45 ns max dout access time after sclk falling edge t 5 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk ns min sclk high pulse width t 7 4 10 ns min sclk to dout valid hold time t 8 5 ns min din setup time prior to sclk falling edge t 9 6 ns min din hold time after sclk falling edge t 10 5 30 ns max sclk falling edge to dout three-state 10 ns min sclk falling edge to dout three-state t power-up 6 1 s max power-up time from full power-down 1 mark/space ratio for sclk input is 40/60 to 60/40. 2 minimum f sclk at which specifications are guaranteed. 3 measured with the load circuit in figure 2 and defined as the time required for the output to cross v ih or v il voltage. 4 measured with a 50 pf load capacitor. 5 t 10 is derived from the measured t ime taken by the data outputs to change 0.5 v when loaded with the circuit in figure 2. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 10 , quoted in the timing characteri stics is the true bus relinquish time of the part and is inde pendent of the bus loading. 6 see the power-up time section. timing diagrams 04350-0-002 200 ai ol 200 ai oh 1.6v to output pin c l 50pf figure 2. load circuit for digital output timing specifications 04350-0-003 sclk v ih v il dout t 4 figure 3. access time after sclk falling edge 04350-0-004 sclk v ih v il dout t 7 figure 4. hold time after sclk falling edge 04350-0-005 sclk 1.6v dout t 10 figure 5. sclk falling edge to dout three-state
ad7911/ad7921 rev. a | page 8 of 28 timing examples figure 6 and figure 7 show some of the timing parameters from the timing specifications section. timing example 1 as shown in figure 7 , when f sclk = 5 mhz and the throughput is 250 ksps, the cycle time is t 2 + 12.5(1/ f sclk ) + t acq = 4 s with t 2 = 10 ns minimum, then t acq is 1.49 s, which satisfies the requirement of 290 ns for t acq . in figure 7 , t acq is comprised of 2.5(1/ f sclk ) + t 10 + t quiet , where t 10 = 30 ns maximum. this allows a value of 960 ns for t quiet , satisfying the minimum requirement of 30 ns. timing example 2 the ad7921 can also operate with slower clock frequencies. as shown in figure 7 , when f sclk = 2 mhz and the throughput rate is 100 ksps, the cycle time is t 2 + 12.5(1/ f sclk ) + t acq = 10 s with t 2 = 10 ns minimum, then t acq is 3.74 s, which satisfies the requirement of 290 ns for t acq . in figure 7 , t acq is comprised of 2.5(1/ f sclk ) + t 10 + t quiet , where t 10 = 30 ns maximum. this allows a value of 2.46 s for t quiet , satisfying the minimum requirement of 30 ns. in this example, as with other slower clock values, the signal might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum t quiet between conversions. in this example, the signal should be fully acquired at approximately point c in figure 7 . 04350-0-006 zero x 12345 13141516 x chn x x x x x x chn x db11 db10 db2 db1 db0 z t 2 t 6 t 4 t 8 t 9 t 3 t 7 t 5 t 10 t 1 t quiet t convert sclk cs dout three-state three-state din b figure 6. ad7921 serial interface timing diagram 04350-0-007 12345 13141516 t quiet t acquisition 1/throughput 12.5(1/f sclk ) t convert bc sclk cs t 10 t 2 figure 7. serial interface timing example
ad7911/ad7921 rev. a | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (a grade) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tsot package ja thermal impedance 207c/w msop package ja thermal impedance 205.9c/w jc thermal impedance 43.74c/w lead temperature soldering reflow (10 s to 30 s) 235 (0/+5)c esd 2 kv 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7911/ad7921 rev. a | page 10 of 28 pin configurations and function descriptions 04350-0-008 v in1 v in0 gnd v dd 8 7 6 5 din 1 sclk 2 cs 3 dout 4 ad7911/ ad7921 8-lead tsot top view (not to scale) figure 8. 8-lead tsot pin configuration 04350-0-034 v dd gnd v in0 v in1 8 7 6 5 dout 1 cs 2 sclk 3 din 4 ad7911/ ad7921 8-lead msop top view (not to scale) figure 9. 8-lead msop pin configuration table 5. pin function descriptions tsot pin no. msop pin no. mnemonic function 1 4 din data in. logic input. the channel to be converted is provided on th is input and is clocked into an internal register on the falling edge of sclk. 2 3 sclk serial clock. logic input. sclk pr ovides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7911/ad7921s conversion process. 3 2 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7911/ad7921 and framing th e serial data transfer. 4 1 dout data out. logic output. the conver sion result from the ad7911/ad7921 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk signal. for the ad7921, the data stream consists of two le ading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 12 bits of conversion data, with msb first. for the ad7911, the data stream consists of two le ading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 10 bits of conversion data, with msb first and two trailing zeros. 5 8 v dd power supply input. the v dd range for the ad7911/ad7921 is from 2.35 v to 5.25 v. 6 7 gnd analog ground. ground referenc e point for all circuitry on the ad7911/ad7921. all analog input signals should be referred to this gnd voltage. 7, 8 6, 5 v in0 , v in1 analog inputs. these two single-ended analog inp ut channels are multiplexe d into the on-chip track- and-hold amplifier. the analog input channel to be converted is selected by writing to the third msb on the din pin. the input range is 0 to v dd .
ad7911/ad7921 rev. a | page 11 of 28 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the ad7911/ ad7921, the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the first code transition (00000) to (00001) from the ideal, that is, agnd + 1 lsb. offset error match the difference in offset error between any two channels. gain error the deviation of the last code transition (111110) to (111111) from the ideal, that is, v ref ? 1 lsb after the offset error has been adjusted out. gain error match the difference in gain error between any two channels. tot a l un a dju s te d e r ror a comprehensive specification that includes gain error, linearity error, and offset error. channel-to-channel isolation a measure of the level of crosstalk between channels. it is measured by applying a full-scale sine wave signal of 20 khz to 500 khz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a 10 khz signal. the figure is given worst case across both channels for the ad7911/ad7921. track-and-hold acquisition time the time required for the output of the track-and-hold amplifier to reach its final value within 1 lsb after the end of conversion. the track-and-hold amplifier returns to track mode at the end of conversion. see the serial interface section for more details. signal-to-noise and distortion ratio (sinad) the measured ratio of signal-to-noise and distortion at the output of the a/d converter. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. signal-to-noise ratio (snr) the measured ratio of signal to noise at the output to the a/d converter. the signal is the rms value of the sine wave input. noise is the rms quantization error within the nyquist bandwidth (fs/2). the rms value of a sine wave is one-half its peak-to-peak value divided by 2, and the rms value for the quantization noise is q/12. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. for an ideal n -bit converter, the snr is defined as db761026 .n.snr + = therefore, for a 12-bit converter, snr is 74 db; for a 10-bit converter, snr is 62 db. however, various error sources in the adc cause the measured snr to be less than the theoretical value. these errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental, which is defined as 1 2 6 2 5 2 4 22 2 v vvvvv thd ++++ = 3 log20)db ( where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specifica- tion is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak.
ad7911/ad7921 rev. a | page 12 of 28 intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7911/ad7921 are tested using the ccif standard, where two input frequencies are used (see fa and fb in the specifications section). in this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second-order and third- order terms are specified separately. the calculation of the intermodulation distortion is as in the thd specification, where it is defined as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in db.
ad7911/ad7921 rev. a | page 13 of 28 typical performance characteristics figure 10 and figure 11 show typical fft plots for the ad7921 and ad7911, respectively, at a 250 ksps sample rate and 100 khz input frequency. figure 12 shows the sinad ratio performance versus the input frequency for various supply voltages while sampling at 250 ksps with a sclk frequency of 5 mhz for the ad7921. figure 13 shows the snr ratio performance versus the input frequency for various supply voltages while sampling at 250 ksps with an sclk frequency of 5 mhz for the ad7921. figure 14 and figure 15 show inl and dnl performance for the ad7921. figure 16 shows a graph of the total harmonic distortion versus the analog input frequency for different source impedances when using a supply voltage of 3.6 v and a sampling rate of 250 ksps. see the analog input section. figure 17 shows a graph of the total harmonic distortion versus the analog input frequency for various supply voltages while sampling at 250 ksps with an sclk frequency of 5 mhz. figure 18 shows the shutdown current versus the voltage supply for different operating temperatures. 5 ?115 ?95 ?75 ?55 ?35 ?15 0 20 40 60 80 100 120 04350-0-009 frequency (khz) snr (db) 8192 point fft v dd = 2.7v f samp = 250ksps f in = 100khz snr = 73.13db sinad = 72.73db thd = ?83.30db sfdr = ?86.15db figure 10. ad7921 dynamic performance at 250 ksps 8192 point fft v dd = 2.7v f samp = 250ksps f in = 100khz snr = 73.13db sinad = 72.73db thd = ?83.30db sfdr = ?86.15db 5 ?115 ?95 ?75 ?55 ?35 ?15 0 20 40 60 80 100 120 04350-0-010 frequency (khz) snr (db) 8192 point fft v dd = 2.7v f samp = 250ksps f in = 100khz snr = 61.75db sinad = 61.74db thd = ?86.24db sfdr = ?84.46db figure 11. ad7911 dynamic performance at 250 ksps ?70.5 ?74.0 ?73.5 ?73.0 ?72.5 ?72.0 ?71.5 ?71.0 10 100 1k 04350-0-011 frequency (khz) sinad (db) v dd = 3.6v v dd = 5.25v v dd = 4.75v v dd = 2.35v v dd = 2.7v figure 12. ad7921 sinad vs. input frequency at 250 ksps ?72.0 ?73.6 ?73.4 ?73.2 ?73.0 ?72.8 ?72.4 ?72.2 ?72.6 10 100 1k 04350-0-012 frequency (khz) snr (db) v dd = 2.35v v dd = 3.6v v dd = 5.25v v dd = 4.75v v dd = 2.7v figure 13. ad7921 snr vs. input frequency at 250 ksps
ad7911/ad7921 rev. a | page 14 of 28 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 4096 3584 3072 2560 2048 1536 1024 512 04350-0-013 code inl error (lsb) v dd = 2.7v f samp = 250ksps temperature = 25 c figure 14. ad7921 inl performance 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 4096 3584 3072 2560 2048 1536 1024 512 04350-0-014 code dnl error (lsb) v dd = 2.7v f samp = 250ksps temperature = 25 c figure 15. ad7921 dnl performance ?95 ?85 ?75 ?65 ?55 ?35 ?25 ?45 10 100 1k 04350-0-015 frequency (khz) thd (db) r in = 1k r in = 500 r in = 100 r in = 50 r in = 10 r in = 0 v dd = 3.6v figure 16. thd vs. analog input frequency for various source impedances ?74 ?76 ?78 ?80 ?82 ?84 ?86 ?88 10 100 1k 04350-0-016 frequency (khz) thd (db) v dd = 2.35v v dd = 3.6v v dd = 5.25v v dd = 4.75v v dd = 2.7v figure 17. thd vs. analog input frequency for various supply voltages 180 160 0 20 40 60 80 100 120 140 2.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 04350-0-017 supply voltage (v) shutdown current (na) temperature = +25 c temperature = +85 c temperature = ?40 c figure 18. shutdown current vs. supply voltage
ad7911/ad7921 rev. a | page 15 of 28 circuit information the ad7911/ad7921 are fast, 2-channel, 10-/12-bit, single supply, analog-to-digital converters (adcs), respectively. the parts can be operated from a 2.35 v to 5.25 v supply. when operated from either a 5 v supply or a 3 v supply, the ad7911/ad7921 are capable of throughput rates of 250 ksps when provided with a 5 mhz clock. the ad7911/ad7921 provide the user with an on-chip track- and-hold, an adc, and a serial interface, all housed in a tiny 8- lead tsot package or an 8-lead msop package, which offer the user considerable space-saving advantages over alternative solutions. the serial clock input accesses data from the parts, controls the transfer of data written to the adc, and provides the clock source for the successive approximation adc. the analog input range is 0 to v dd . an external reference is not required for the adc, and neither is there a reference on-chip. the reference for the ad7911/ad7921 is derived from the power supply and, therefore, gives the widest dynamic input range. the ad7911/ad7921 feature a power-down option that allows power saving between conversions. the power-down feature is implemented across the standard serial interface as described in the modes of operation section. converter operation the ad7911/ad7921 are 10-/12-bit successive approximation adcs based around a charge redistribution dac. figure 19 and figure 20 show simplified schematics of the adc. figure 19 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on the selected v in channel. 04350-0-018 comparator acquisition phase v dd /2 sw2 sw1 v in0 v in1 sampling capacitor agnd a b charge redistribution dac control logic figure 19. adc acquisition phase when the adc starts a conversion (see figure 20 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 21 shows the adc transfer function. 04350-0-019 comparator conversion phase v dd /2 sw2 sw1 v in0 v in1 sampling capacitor agnd a b charge redistribution dac control logic figure 20. adc conversion phase adc transfer function the output coding of the ad7911/ad7921 is straight binary. the designed code transitions occur at the successive integer lsb values, that is, 1 lsb, 2 lsb, and so on. the lsb size is v dd /4096 for the ad7921 and v dd /1024 for the ad7911. the ideal transfer characteristic for the ad7911/ad7921 is shown in figure 21 . 04350-0-020 000...000 0v adc code analog input 111...111 000...001 111...000 011...111 111...110 000...010 1lsb = v dd /4096 (ad7921) 1lsb = v dd /1024 (ad7911) +v dd ? 1lsb 1lsb figure 21. ad7911/ad7921 transfer characteristic
ad7911/ad7921 rev. a | page 16 of 28 typical connection diagram figure 22 shows a typical connection diagram for the ad7911/ ad7921. v ref is taken internally from v dd and as such v dd should be well decoupled. this provides an analog input range of 0 v to v dd . the conversion result is output in a 16-bit word with two leading zeros, followed by the channel identifier bit that identifies the channel converted, followed by an invalid bit that matches up to the channel converted, followed by the msb of the 12-bit or 10-bit result. for the ad7911, the 10-bit result is followed by two trailing zeros. see the serial interface section. alternatively, because the supply current required by the ad7911/ad7921 is so low, a precision reference can be used as the supply source to the ad7911/ad7921. a ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) can be used to supply the required voltage to the adc (see figure 22 ). this configuration is especially useful, if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v (for example, 15 v). the ref19x outputs a steady voltage to the ad7911/ad7921. if the low dropout ref193 is used, the current it needs to supply to the ad7911/ ad7921 is typically 1.5 ma. when the adc is converting at a rate of 250 ksps, the ref193 needs to supply a maximum of 2 ma to the ad7911/ad7921. the load regulation of the ref193 is typically 10 ppm/ma (ref193, v s = 5 v), which results in an error of 20 ppm (60 v) for the 2 ma drawn from it. this corresponds to a 0.082 lsb error for the ad7921 with v dd = 3 v from the ref193 and a 0.061 lsb error for the ad7911. for applications where power consumption is a concern, the power-down mode of the adc and the sleep mode of the ref19x reference should be used to improve power perform- ance. see the modes of operation section. 04350-0-021 ad7911/ ad7921 v dd v in0 serial interface 0 v to v dd input c/ p v in1 gnd sclk cs din dout 0.1 f 10 f 1 f tant 0.1 f 680nf 3v 5v supply 1.5ma ref193 figure 22. ref193 as power supply to ad7911/ad7921 table 6 provides some typical performance data with various references used as a v dd source and a 50 khz input tone under the same setup conditions. table 6. ad7921 performance for various voltage references ic reference tied to v dd ad7921 snr performance (db) ad780 at 3 v ?73 ref193 ?72.42 adr433 ?72.9 ad780 at 2.5 v ?72.86 ref192 ?72.27 adr421 ?72.75 analog input figure 23 shows an equivalent circuit of the analog input structure of the ad7911/ad7921. the two diodes, d1 and d2, provide esd protection for the analog input. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mv, because this would cause these diodes to become forward biased and start conducting current into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the part is 10 ma. 04350-0-022 c1 6pf c2 20pf r1 d1 d2 conversion phase?switch open track phase?switch closed v dd v in figure 23. equivalent analog input circuit the capacitor c1 in figure 23 is typically about 6 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a track- and-hold switch and also includes the on resistance of the input multiplexer. this resistor is typically about 100 . the capacitor c2 is the adc sampling capacitor and has a capacitance of 20 pf typically. for ac applications, removing high frequency components from the analog input signal is recommended using a band-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances can significantly affect the ac performance of the adc. this might necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application.
ad7911/ad7921 rev. a | page 17 of 28 din input table 7 provides some typical performance data with various op amps used as the input buffer, and a 50 khz input tone under the same setup conditions. the channel to be converted on in the next conversion is selected by writing to the din pin. data on the din pin is loaded into the ad7911/ad7921 on the falling edge of sclk. the data is transferred into the part on the din pin at the same time that the conversion result is read from the part. table 7. ad7921 performance for various input buffers op amp in the input buffer ad7921 snr performance (db) 50 khz input , v dd = 3.6 v single op amps ad8038 ?72.79 ad8510 ?72.35 ad8021 ?72.2 dual op amps ad712 ?72.68 only the third bit of the din word is used; the rest are ignored by the adc. the third msb is the channel identifier bit, which identifies the channel to be converted on in the next conversion, v in0 (chn = 0) or v in1 (chn = 1). 04350-0-023 lsb msb x x chn x don't care ad8022 ?72.88 when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases and performance degrades (see figure 16 ). figure 24. ad7911/ad7921 din word dout output the conversion result from the ad7911/ad7921 is provided on this output as a serial data stream. the bits are clocked out on the sclk falling edge at the same time that the conversion is taking place. digital inputs the serial data stream for the ad7921 consists of two leading zeros followed by the bit that identifies the channel converted, an invalid bit that matches up to the channel identifier bit, and the 12-bit conversion result with msb provided first. the digital inputs applied to the ad7911/ad7921 are not limited by the maximum ratings that limit the analog input. instead, the digital inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog input. for example, if the ad7911/ad7921 are operated with a v dd of 3 v, then 5 v logic levels could be used on the digital inputs. how- ever, it is important to note that the data output on dout still has 3 v logic levels when v dd = 3 v. another advantage of sclk, din, and cs not being restricted by the v dd + 0.3 v limit is that power supply sequencing issues are avoided. if cs , din, or sclk are applied before v dd , then there is no risk of latch-up as there would be on the analog inputs, if a signal greater than 0.3 v were applied prior to v dd . for the ad7911, the serial data stream consists of two leading zeros followed by the bit that identifies the channel converted, an invalid bit that matches up to the channel identifier bit, and the 10-bit conversion result with msb provided first, followed by two trailing zeros. 04350-0-024 lsb ad7911 msb 00 0 0 chn x conversion result ad7921 0 0 chn x conversion result figure 25. ad7911/ad7921 dout word
ad7911/ad7921 rev. a | page 18 of 28 modes of operation the two modes of operation of the ad7911/ad7921 are normal mode and power-down mode. the mode of operation is selected by controlling the logic state of the cs signal. the point at which cs is pulled high after the conversion has been initi- ated determines whether the ad7911/ad7921 enter power- down mode. similarly, if already in power-down mode, cs can control whether the device returns to normal operation or remains in power-down mode. power-down mode is designed to provide flexible power management options and to optimize the ratio of power dissipation to throughput rate for different application requirements. normal mode normal mode is intended for the fastest throughput rate performance. the user does not have to worry about any power-up time, because the ad7911/ad7921 remain fully powered all the time. figure 26 shows the operation of the ad7911/ad7921 in this mode. the conversion is initiated on the falling edge of cs , as described in the section. to ensure that the part remains fully powered up at all times, serial interface cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge but before the end of t convert , the part remains powered- up, but the conversion is terminated and dout goes back into three-state. for the ad7911/ad7921, a minimum of 14 and 16 serial clock cycles, respectively, are needed to complete the conversion and access the complete conversion result. cs can idle high until the next conversion or can idle low until cs returns high sometime prior to the next conversion (effectively idling cs low). once a data transfer is complete (dout has returned to three-state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. power-down mode power-down mode is intended for use in applications where slower throughput rates are required. either the adc is powered down between each conversion, or a series of conversions can be performed at a high throughput rate and then the adc is powered down for a relatively long duration between these bursts of several conversions. when the ad7911/ad7921 are in power-down mode, all analog circuitry is powered down. to enter power-down mode, the conversion process must be interrupted by bringing cs high any time after the second falling edge of sclk and before the 10th falling edge of sclk, as shown in . once figure 27 cs has been brought high in this window of sclks, then the part enters power-down mode, the conversion that was initiated by the falling edge of cs is terminated, and dout goes back into three-state. if cs is brought high before the second sclk falling edge, then the part remains in normal mode and does not power down. this helps to avoid accidental power-down due to glitches on the cs line. to exit this mode of operation and power the ad7911/ad7921 up again, a dummy conversion is performed. on the falling edge of cs , the device begins to power up and continues to power up as long as cs is held low until after the falling edge of the 10th sclk. the device is fully powered up once 16 sclks have elapsed and valid data results from the next conversion, as shown in . if figure 28 cs is brought high before the 10th falling edge of sclk, then the ad7911/ad7921 go back into power- down mode. this helps to avoid accidental power-up due to glitches on the cs line or an inadvertent burst of 8 sclk cycles while cs is low. therefore, although the device might begin to power up on the falling edge of cs , it powers down again on the rising edge of cs , as long as this occurs before the 10th sclk falling edge. 04350-0-025 cs 1 10 12 14 16 1 10 12 14 16 ad7911/ad7921 sclk din dout channel for next conversion channel for next conversion conversion result conversion result figure 26. normal mode operation
ad7911/ad7921 rev. a | page 19 of 28 04350-0-026 invalid data three-state invalid data three-state 1 cs sclk din dout 21 01 6 figure 27. entering power- down mode 04350-0-027 11 0 the part begins to power up the part goes into track the part is fully powered up with v in fully acquired 5 a 16 1 16 sclk cs din channel for next conversion channel for next conversion dout invalid data conversion result figure 28. exiting power-down mode power-up time the power-up time of the ad7911/ad7921 is 1 s, which means that with any frequency of sclk up to 5 mhz, one dummy cycle is always sufficient to allow the device to power up. once the dummy cycle is complete, the adc is fully powered up and the input signal is acquired properly. the quiet time, t quiet , must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of cs . when running at a 250 ksps throughput rate, the ad7911/ad7921 power up and acquire a signal within 1 lsb in one dummy cycle. when powering up from power-down mode with a dummy cycle, as in figure 28 , the track-and-hold that was in hold mode while the part was powered down returns to track mode on the fifth sclk falling edge that the part receives after the falling edge of cs . this is shown as point a in . at this point, the part starts to acquire the signal on the channel selected in the current dummy conversion. figure 28 although at any sclk frequency one dummy cycle is sufficient to power up the device and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully. 1s is sufficient to power up the device and acquire the input signal. for example, if a 5 mhz sclk frequency was applied to the adc, the cycle time would be 3.2 s. in one dummy cycle, 3.2 s, the part would be powered up and v in acquired fully. however, after 1 s with a 5 mhz sclk, only 5 sclk cycles would have elapsed. at this stage, the adc would be fully powered up. in this case, cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the ad7911/ad7921, the adc can power up in either power-down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. likewise, if the user wants to keep the part in power-down mode while not in use and to power up in power-down mode, then the dummy cycle can be used to ensure that the device is in power-down mode by executing a cycle such as that shown in figure 27 . once supplies are applied to the ad7911/ad7921, the power- up time is the same as when powering up from the power-down mode. it takes the part approximately 1 s to power up fully in normal mode. it is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. when the adc powers up initially after supplies are applied, the track-and-hold is in hold. it returns to track on the fifth sclk falling edge that the part receives after the falling edge of cs .
ad7911/ad7921 rev. a | page 20 of 28 power vs. throughput rate by using the power-down mode on the ad7911/ad7921 when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 29 shows how, as the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. for example, if the ad7911/ad7921 are operating in a continuous sampling mode with a throughput rate of 50 ksps and a sclk of 5 mhz (v dd = 5 v) and the devices are placed in power-down mode between conversions, then the power consumption is calculated as follows. the power dissipation during normal operation is 20 mw (v dd = 5 v). if one dummy cycle powers up the part between conversions (3.2 s), and the remaining conversion time is another cycle (3.2 s), then the ad7911/ad7921 dissipate 20 mw for 6.4 s during each conversion cycle. if the throughput rate is 50 ksps and the cycle time is 20 s, then the average power dissipated during each cycle is (6.4/20) (20 mw) = 6.4 mw if v dd = 3 v, sclk= 5 mhz, and the device is again in power- down mode between conversions, then the power dissipation during normal operation is 6 mw. the ad7911/ad7921 now dissipate 6 mw for 6.4 s during each conversion cycle. with a throughput rate of 50 ksps, the average power dissipated during each cycle is (6.4/20) (6 mw) = 1.92 mw in the previous examples, the power dissipation when the part is in power-down mode has not been taken into account, because the shutdown current is so low that it does not have any effect on the overall power dissipation value. figure 29 shows the power consumption versus throughput rate when using the power-down mode between conversions with both 5 v and 3 v supplies. power-down mode is intended for use with throughput rates of approximately 120 ksps and under, because higher sampling rates do not have a power saving in power-down mode. 0.01 100 10 1 0.1 0 135120105907560453015 04350-0-035 throughput (ksps) power (mw) v dd = 5v, sclk = 5mhz v dd = 3v, sclk = 5mhz figure 29. power consumption vs. throughput rate
ad7911/ad7921 rev. a | page 21 of 28 serial interface figure 30 and figure 31 show the detailed timing diagrams for serial interfacing to the ad7921 and ad7911, respectively. the serial clock provides the conversion clock and also controls the transfer of information from the ad7911/ad7921 during conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode, takes the bus out of three-state, the analog input is sampled at this point, and the conversion is initiated. for the ad7921, the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track- and-hold goes back into track on the next sclk rising edge, as shown in figure 30 at point b. on the 16th sclk falling edge, the dout line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, then the conversion is terminated and the dout line goes back into three-state. otherwise, dout returns to three-state on the 16th sclk falling edge, as shown in . sixteen serial clock cycles are required to perform the conversion process and to access data from the ad7921. figure 30 for the ad7911, the conversion requires 14 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track- and-hold goes back into track on the next sclk rising edge, as shown in figure 31 at point b. if the rising edge of cs occurs before 14 sclks have elapsed, then the conversion is terminated and the dout line goes back into three-state. if 16 sclks are considered in the cycle, dout returns to three-state on the 16th sclk falling edge, as shown in . figure 31 cs going low clocks out the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the second leading zero. therefore, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge. in that case, the first falling edge of sclk clocks out the second leading zero and it can be read in the first rising edge. however, the first leading zero that is clocked out when cs goes low is missed, unless it is not read in the first falling edge. the 15th falling edge of sclk clocks out the last bit and it can be read in the 15th rising sclk edge. if cs goes low just after the sclk falling edge has elapsed, cs clocks out the first leading zero as before and it can be read in the sclk rising edge. the next sclk falling edge clocks out the second leading zero and it can be read in the following rising edge. 04350-0-029 zero x 12345 13141516 x chn x x x x x x chn x db11 db10 db2 db1 db0 z t 2 t 6 t 4 t 8 t 9 t 3 t 7 t 5 t 10 t 1 t quiet t convert sclk cs dout three-state three-state din b figure 30. ad7921 serial interface timing diagram 04350-0-030 zero x 12345 13141516 x chn x x x x x x chn x db9 db8 db0 zero zero z t 2 t 6 t 4 t 8 t 9 t 3 t 7 t 5 t 10 t 1 t quiet t convert sclk cs dout three-state three-state two trailing zeros din b figure 31. ad7911 serial interface timing diagram
ad7911/ad7921 rev. a | page 22 of 28 microprocessor interfacing the serial interface on the ad7911/ad7921 allows the parts to be directly connected to a range of microprocessors. this section explains how to interface the ad7911/ad7921 with some of the more common microcontroller and dsp serial interface protocols. ad7911/ad7921 to tms320c541 interface the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7911/ad7921. the cs input allows easy interfacing between the tms320c541 and the ad7911/ad7921 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode (fsm = 1 in the serial port control register, spc) with the internal serial clock clkx (mcm = 1 in the spc register) and the internal frame signal (txm = 1 in the spc register); therefore, both pins are configured as outputs. for the ad7921, the word length should be set to 16 bits (fo = 0 in the spc register). this dsp allows frames with a word length of 16 bits or 8 bits only. in the ad7911, therefore, where 14 bits are required, the fo bit should be set up to 16 bits, and 16 sclks are needed. for the ad7911, two trailing zeros are clocked out in the last two clock cycles. the values in the spc register are as follows: fo = 0 fsm = 1 mcm = 1 txm = 1 to implement the power-down mode on the ad7911/ad7921, the format bit, fo, can be set to 1, which sets the word length to 8 bits. the connection diagram is shown in figure 32 . note that, for signal processing applications, the frame synchronization signal from the tms320c541 must provide equidistant sampling. ad7911/ ad7921* tms320c541* clkx dr fsx fsr sclk dout cs clkr dx din 04350-0-031 *additional pins omitted for clarity figure 32. interfacing to the tms320c541 ad7911/ad7921 to adsp-218x the adsp-218x family of dsps are interfaced directly to the ad7911/ad7921 without any glue logic required. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right-justify data isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, set up rfs as an input itfs = 1, set up tfs as an output slen = 1111, 16 bits for the ad7921 slen = 1101, 14 bits for the ad7911 to implement the power-down mode, slen should be set to 0111 to issue an 8-bit sclk burst. the connection diagram is shown in figure 33 . the adsp-218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described previously. the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc and, under certain conditions, equidistant sampling might not be achieved. ad7911/ ad7921* adsp-218x* sclk rfs tfs sclk cs dr dout dt din 04350-0-032 *additional pins omitted for clarity figure 33. interfacing to the adsp-218x the timer registers are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and, therefore, the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, that is, tx0 = ax0, the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high again before transmission starts. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data might be transmitted, or it might wait until the next clock edge.
ad7911/ad7921 rev. a | page 23 of 28 for example, the adsp-2189 has a master clock frequency of 40 mhz. if the sclkdiv register is loaded with the value of 3, then an sclk of 5 mhz is obtained, and eight master clock periods elapse for every one sclk period. depending on the throughput rate selected, if the timer register is loaded with the value 803 (803 + 1 = 804), then 100.5 sclk occur between interrupts and subsequently between transmit instructions. this situation results in nonequidistant sampling, because the transmit instruction occurs on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n , then equidistant sampling is implemented by the dsp. ad7911/ad7921 to dsp563xx interface the connection diagram in figure 34 shows how the ad7911/ ad7921 can be connected to the ssi (synchronous serial interface) of the dsp563xx family of dsps from motorola. the ssi is operated in synchronous and normal mode (syn = 1 and mod = 0 in the control register b, crb) with internally generated word frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in the crb). set the word length in the control register a (cra) to 16 by setting bits wl2 = 0, wl1 = 1, and wl0 = 0 for the ad7921. this dsp does not offer the option for a 14-bit word length, so the ad7911 word length is set up to 16 bits like the ad7921. for the ad7911, the conversion process uses 16 sclk cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. to implement the power-down mode on the ad7911/ad7921, the word length can be changed to 8 bits by setting bits wl2 = 0, wl1 = 0, and wl0 = 0 in cra. the fsp bit in the crb register can be set to 1, which means that the frame goes low and a conversion starts. likewise, by means of the bits scd2, sckd, and shfd in the crb register, the pin sc2 (the frame sync signal) and sck in the serial port are configured as outputs, and the msb is shifted first. the values are as follows: mod = 0 syn = 1 wl2, wl1, wl0 depend on the word length fsl1 = 0, fsl0 = 0 fsp = 1, negative frame sync scd2 = 1 sckd = 1 shfd = 0 note that, for signal processing applications, the frame synchronization signal from the dsp563xx must provide equidistant sampling. ad7911/ ad7921* dsp563xx* sck sclk srd dout std din sc2 cs 04350-0-033 *additional pins omitted for clarity figure 34. interfacing to the dsp563xx
ad7911/ad7921 rev. a | page 24 of 28 application hints grounding and layout the printed circuit board that houses the ad7911/ad7921 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes, because it gives the best shielding. digital and analog ground planes should be joined at only one place. if the ad7911/ ad7921 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7911/ad7921. avoid running digital lines under the device, because these couple noise onto the die. the analog ground plane should be allowed to run under the ad7911/ad7921 to avoid noise coupling. the power supply lines to the ad7911/ad7921 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast-switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also very important. the analog supply should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to agnd. to achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum with short track lengths connecting the respective pins.
ad7911/ad7921 rev. a | page 25 of 28 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 35. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 13 56 2 8 4 7 2.90 bsc pin 1 indicator 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.10 max * 0.90 0.87 0.84 seating plane * 1.00 max 0.20 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc * compliant to jedec standards mo-193-ba with the exception of package height and thickness. figure 36. 8-lead thin small outline transistor package [tsot] (uj-8) dimensions shown in millimeters ordering guide model 1 temperature range linearity error (lsb) 2 package description package option branding ad7911armz ?40c to +85c 0.5 max 8-lead msop rm-8 #c1j ad7911armz-reel ?40c to +85c 0.5 max 8-lead msop rm-8 #c1j ad7911arm-reel7 ?40c to +85c 0.5 max 8-lead msop rm-8 #c1j ad7911armz-reel7 ?40c to +85c 0.5 max 8-lead msop rm-8 #c1j AD7911AUJZ-R2 ?40c to +85c 0.5 max 8-lead tsot uj-8 #c1j ad7911aujz-reel7 ?40c to +85c 0.5 max 8-lead tsot uj-8 #c1j ad7921armz ?40c to +85c 1.5 max 8-lead msop rm-8 #c1k ad7921armz-reel ?40c to +85c 1.5 max 8-lead msop rm-8 #c1k ad7921armz-reel7 ?40c to +85c 1.5 max 8-lead msop rm-8 #c1k ad7921aujz-r2 ?40c to +85c 1.5 max 8-lead tsot uj-8 #c1k ad7921aujz-reel7 ?40c to +85c 1.5 max 8-lead tsot uj-8 #c1k 1 z = rohs compliant part. 2 linearity error here refers to integral nonlinearity.
ad7911/ad7921 rev. a | page 26 of 28 notes
ad7911/ad7921 rev. a | page 27 of 28 notes
ad7911/ad7921 rev. a | page 28 of 28 notes ?2004C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04350C0C5/11(a)

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